1. Field of the Invention
This invention relates generally to memory devices, and more particularly, to an electrically programmable and erasable memory device and method for making the same.
2. Discussion of the Related Art
FIGS. 1-4 illustrate a prior art electrically programmable and erasable memory device and a method of fabrication thereof. Initially, with reference to FIG. 1, a substrate, for example a P type silicon substrate 30, is provided. A silicon dioxide (SiO2) layer 32 is grown thereon, and successive layers of silicon nitride (SiN) 34, silicon dioxide (SiO2) 36, silicon nitride (SiN) 38, and P+ polysilicon 40 are deposited. A layer of photoresist is then provided on the polysilicon layer 40, and portions of the photoresist layer are removed using a well known procedure, so that the remaining photoresist 42 is provided on the polysilicon layer 40 as shown in FIG. 1. Using this remaining photoresist 42 as a mask, an etching step is undertaken to remove portions of the layers 40, 38, 36, 34, 32, forming a stack 44 including remaining layers of silicon dioxide 32A, silicon nitride 34A, silicon dioxide 36A, silicon nitride 38A and polysilicon 40A on the substrate 30 (FIG. 2).
An ion implantation step 45 is undertaken, in this example using n-type dopant, to form N+ source 46 and drain 48 in the substrate 40, the photoresist 42 and the layers therebeneath acting as a mask. (FIG. 3) The photoresist 42 is then removed, resulting in the structure 49 shown in FIG. 4.
This structure 49 is an electrically programmable and erasable memory device wherein the silicon dioxide layer 32A is a tunneling gate layer, the silicon nitride layer 34A is a storage layer (floating gate), the silicon dioxide layer 36A and silicon nitride layer 38A together form a dielectric 39 between the storage layer 34A and the polysilicon layer 40A, and the polysilicon layer 40A is the control gate of the device 49.
In programming the device 49, as is well known, a positive voltage is applied to the drain 48, and the source 46 is grounded. Applying a positive voltage pulse of sufficient magnitude to the control gate 40A causes electrons to travel from the substrate 30 through the tunneling gate layer 32A and into the storage layer 34A, such electrons stored in the storage layer 34A causing the device 49 to be in its programmed state. In the erasing of the device 49, a positive voltage is applied to the control gate 40A, while the substrate 30, source 46 and drain 48 are grounded. Applying a positive voltage pulse of sufficient magnitude to the control gate 40A causes holes in the gate 40A to travel through the dielectric 39 (which includes layers 36A, 38A) and into the storage layer 34A, wherein they are combined with electrons stored in the storage layer 34A to cause the device 49 to be in its erased state.
While the device 49 thus far shown and described is highly efficient in operation, it will be understood that it is always desirable to improve operational speed thereof. In furtherance thereof, the present approach improves erase speed as compared to the prior device as will be shown and described.